Low temperature lithographically patterned metal oxide transistors for large area electronics
Name
756403443-MIT.pdf
Description
Full printable version
Size
20.22 MB
Format
Adobe PDF
Checksum (MD5)
517e0ad7ee86b7ed6f803cb3e3ac2e15
Author(s)
Wang, Annie I. (Annie I-Jen), 1981-
Advisor(s)
Akintunde I. Akinwande.
Date Issued
2011
Publisher
Massachusetts Institute of Technology
Abstract
Optically transparent, wide bandgap metal oxide semiconductors are a promising candidate for large-area electronics technologies that require lightweight, temperature-sensitive flexible substrates. Because these thin films retain relatively high carrier mobilities even in an amorphous state, metal oxide-based field effect transistors (FETs) can be processed at near-room temperatures. Compared to amorphous silicon FETs, which are the dominant technology used in display backplanes, metal oxide FETs have been demonstrated with higher charge carrier mobilities, higher current densities, and faster response performance. In this thesis we present a low-temperature ('1000C), scalable, fully lithographic process for top-gate, bottom-contact amorphous zinc indium oxide FETs using parylene, a room-temperature-deposited CVD polymer, as gate dielectric. Electrical characteristics were compared for FETs of varying device dimensions (W, L) using a standard set of extracted device parameters. We show in both simulation and experiment that the FET threshold voltage can be modified by varying the channel thickness alone, without requiring the additional complexity of multiple channel materials or different dopings. The baseline lithographic process was further developed to enable the integration of FETs of different channel thicknesses, and hence threshold voltages, on a single substrate. The availability of FETs with different threshold voltages allows the implementation of enhancement-depletion (E/D) logic circuits that have faster speeds and smaller device areas than single-VT topologies. Using the two-VT lithographic process, we fabricated integrated E/D inverters that operate at VDD as low as 3V with gains > 20 and symmetric noise margins ~1.2V. Furthermore, we demonstrated integrated 11-stage and 21-stage E/D ring oscillators that operated rail-to-rail at VDD= 3V and maintained oscillation for VDD as low as 1.7V. These results demonstrate the potential for low VDD metal oxide-based integrated circuits fabricated in a low temperature budget, fully lithographic process for large-area transparent electronics.
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 167-184).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
M.I.T. theses are protected by
copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
permission. See provided URL for inquiries about permission.
copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
permission. See provided URL for inquiries about permission.
Persistent DSpace Link
