Concurrent gate-level circuit simulation
Name
703282973-MIT.pdf
Description
Full printable version
Size
3.14 MB
Format
Adobe PDF
Checksum (MD5)
74c5a928cd6fda29146188f7e4d5af02
Author(s)
Shelly, Jacinda R. (Jacinda Rene)
Advisor(s)
Christopher J. Terman.
Alternative Title
Concurrent Gsim
Date Issued
2010
Publisher
Massachusetts Institute of Technology
Abstract
In the last several years, parallel computing on multicore processors has transformed from a niche discipline relegated primarily to scientific computing into a standard component of highperformance personal computers. At the same time, simulating processors prior to manufacture has become increasingly time-consuming due to the increasing number of gates on a single chip. However, writing parallel programs in a way that significantly improves performance can be a difficult task. In this thesis, I outline principles that must be considered when running good gate-level circuit simulations in parallel. I also analyze a test circuit's performance in order to quantitatively demonstrate the benefit of considering these principles in advance of running simulations.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 42).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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