Judicious Thread Migration When Accessing Distributed Shared Caches
Name
Devadas-Judicious thread.pdf
Size
278.96 KB
Format
Adobe PDF
Checksum (MD5)
250c6483d97403f325e522a409770c58
Author(s)
Shim, Keun Sup
Lis, Mieszko
Khan, Omer
Devadas, Srinivas
Date Issued
January 2012
Journal
Proceedings of the Third Workshop on Computer Architecture and Operating System Co-design (CAOS), 2012
Citation
Shim, Keun Sup, Mieszko Lis, Omer Khan, and Srinivas Devadas. Judicious Thread Migration When Accessing Distributed Shared Caches." in Proceedings of the Third Workshop on Computer Architecture and Operating System Co-design (CAOS), 2012 January 25, 2012, Paris, France.
Version
Author's final manuscript
Abstract
Chip-multiprocessors (CMPs) have become the mainstream chip design in recent years; for scalability reasons, designs with high core counts tend towards tiled CMPs with physically distributed shared caches. This naturally leads to a Non-Uniform Cache Architecture (NUCA) design, where on chip access latencies depend on the physical distances between requesting cores and home cores where the data is cached. Improving data locality is thus key to performance, and several studies have addressed this problem using data replication and data migration. In this paper, we consider another mechanism, hardware level thread migration. This approach, we argue, can better exploit shared data locality for NUCA designs by effectively replacing multiple round-trip remote cache accesses with a smaller number of migrations. High migration costs, however, make it crucial to use thread migrations judiciously; we therefore propose a novel, on-line prediction scheme which decides whether to perform a remote access (as in traditional NUCA designs) or to perform a thread migration at the instruction level. For a set of parallel benchmarks, our thread migration predictor improves the performance by 18% on average and at best by 2.3X over the standard NUCA design that only uses remote accesses.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike 3.0
Persistent DSpace Link
DOI of Published Version
http://projects.csail.mit.edu/caos/caos_2012.pdf
