Communication-Minimal Partitioning of Parallel Loops and Data Arrays for Cache-Coherent Distributed -Memory Multiprocess
Name
MIT-LCS-TM-522.pdf
Size
163.85 KB
Format
Adobe PDF
Checksum (MD5)
ab0cfc0b243000134a77052e43f3b92f
Author(s)
Barua, Rajeev
Kranz, David
Agarwal, Anant
Date Issued
January 1995
Series/Report no.
MIT-LCS-TM-522
Abstract
Harnessing the full performance potential of cache-coherent distributed shared memory multiprocessors without inordinate user effort requires a compilation technology that can automatically manage multiple levels of memory hierarchy. This paper describes a working compiler for such machines that automatically partitions loops and data arrays to optimize locality of access.
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