A low jitter programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning loop
Name
Helal-2008-A Low Jitter Program.pdf
Size
1.47 MB
Format
Adobe PDF
Checksum (MD5)
8dd47c91aad479c570b2d61b56e43798
Author(s)
Perrott, Michael H.
Johnson, Kerwin
Hsu, Chun-Ming
Helal, Belal M.
Date Issued
May 2009
Journal
IEEE Journal of Solid-State Circuits
Publisher
Institute of Electrical and Electronics Engineers
Citation
Helal, B.M. et al. “A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop.” Solid-State Circuits, IEEE Journal of 44.5 (2009): 1391-1400. © 2009 IEEE
Version
Final published version
Abstract
This paper introduces a pulse injection-locked oscillator (PILO) that provides low jitter clock multiplication of a clean input reference clock. A mostly-digital feedback circuit provides continuous tuning of the oscillator such that its natural frequency is locked to the injected frequency. The proposed system is demonstrated with a prototype consisting of a custom 0.13 mum integrated circuit with active area of 0.4 mm[superscript 2] and core power of 28.6 mW, along with an FPGA, a discrete DAC and a simple RC filter. Using a low jitter 50 MHz reference input, the PILO prototype generates a 3.2 GHz output with integrated phase noise, reference spur, and estimated deterministic jitter of 130 fs (rms), -63.9 dBc, and 200 fs (peak-to-peak), respectively.
Subjects
time to digital converter
reference spur
pulse
phase locked loop
integer-N
injection locked oscillator
gated ring oscillator
deterministic jitter
correlation
correlated double sampling
TDC
Subharmonic
PLL
PILO
GRO
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
http://dx.doi.org/10.1109/JSSC.2009.2015816
