Scalable directoryless shared memory coherence using execution migration
Name
MIT-CSAIL-TR-2010-053.pdf
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724.59 KB
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Checksum (MD5)
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Author(s)
Lis, Mieszko
Shim, Keun Sup
Cho, Myong Hyon
Khan, Omer
Devadas, Srinivas
Advisor(s)
Srini Devadas
Date Issued
November 22, 2010
Series/Report no.
MIT-CSAIL-TR-2010-053
Abstract
We introduce the concept of deadlock-free migration-based coherent shared memory to the NUCA family of architectures. Migration-based architectures move threads among cores to guarantee sequential semantics in large multicores. Using a execution migration (EM) architecture, we achieve performance comparable to directory-based architectures without using directories: avoiding automatic data replication significantly reduces cache miss rates, while a fast network-level thread migration scheme takes advantage of shared data locality to reduce remote cache accesses that limit traditional NUCA performance. EM area and energy consumption are very competitive, and, on the average, it outperforms a directory-based MOESI baseline by 6.8% and a traditional S-NUCA design by 9.2%. We argue that with EM scaling performance has much lower cost and design complexity than in directory-based coherence and traditional NUCA architectures: by merely scaling network bandwidth from 128 to 256 (512) bit flits, the performance of our architecture improves by an additional 8% (12%), while the baselines show negligible improvement.
Subjects
multicore
memory architecture
cache coherence
nuca
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