A sampling jitter tolerant continuous-time pipeline ADC
Name
1201912645-MIT.pdf
Size
3.72 MB
Format
Adobe PDF
Checksum (MD5)
07c264ddec3d1436ab904869f61a76aa
Author(s)
Mittal, Rishabh.
Advisor(s)
Anantha P. Chandrakasan and Hae-Seung Lee.
Date Issued
2020
Publisher
Massachusetts Institute of Technology
Abstract
A sampling jitter tolerant continuous-time (CT) pipeline ADC has been presented in this thesis. In conventional discrete-time (DT) pipeline ADCs, the input is sampled upfront. The improvements in the bandwidth and sampling speed due to CMOS scaling have brought the deleterious effects of sampling clock jitter to the forefront. Any jitter in the sampling clock edge adds a random error to the input signal thereby limiting the maximum achievable signal-to-noise ratio (SNR), and hence the effective resolution of the ADC. The effect of sampling clock jitter has been considered fundamental. In the proposed ADC, we do not sample the input upfront. Rather, we sample the residue from the first stage. Since the residue is bandlimited and has a small magnitude, therefore it will have a smaller derivative. Hence, the sensitivity to the clock jitter will be greatly reduced.
Description
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, February, 2020
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 43-45).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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