A 0.68V 0.68mW 2.4GHz PLL for ultra-low power RF systems
Name
PLL_low_voltage_r8.pdf
Description
Final submission by author
Size
741.25 KB
Format
Adobe PDF
Checksum (MD5)
5faf45ea3419a947d5e385c5591b7719
Author(s)
Paidimarri, Arun
Ickes, Nathan
Chandrakasan, Anantha P.
Date Issued
May 2015
Journal
Proceedings of the 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Paidimarri, Arun, Nathan Ickes, and Anantha P. Chandrakasan. “A 0.68V 0.68mW 2.4GHz PLL for Ultra-Low Power RF Systems.” 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (May 2015).
Version
Author's final manuscript
Abstract
A 2.4GHz PLL consuming 0.68mW has been implemented in 65nm LPCMOS for use in ultra-low power Bluetooth Low Energy (BLE) applications. VCO, charge pump and dynamic flip-flop design optimization allow low voltage operation at 0.68V, bringing down dynamic power. The integer-N PLL covers all BLE channels and has a phase noise of −110dBc/Hz at 1MHz offset. To extend operation to extremely low duty cycles, extensive power gating is applied to bring the leakage power down to 170pW.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology. Microsystems Technology Laboratories
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1109/RFIC.2015.7337789
