Extending hardware transactional memory capacity via rollback-only transactions and suspend/resume
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446_2019_363_ReferencePDF.pdf
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Author(s)
Issa, Shady
Felber, Pascal
Matveev, Alexander
Romano, Paolo
Date Issued
November 11, 2019
Publisher
Springer Berlin Heidelberg
Version
Author's final manuscript
Abstract
Abstract
Transactional memory (TM) aims at simplifying concurrent programming via the familiar abstraction of atomic transactions. Recently, Intel and IBM have integrated hardware based TM (HTM) implementations in commodity processors, paving the way for the mainstream adoption of the TM paradigm. Yet, existing HTM implementations suffer from a crucial limitation, which hampers the adoption of HTM as a general technique for regulating concurrent access to shared memory: the inability to execute transactions whose working sets exceed the capacity of CPU caches. In this article we propose P8TM, a novel approach that mitigates this limitation on IBM’s POWER8 architecture by leveraging a key combination of hardware and software techniques to support different execution paths. P8TM also relies on self-tuning mechanisms aimed at dynamically switching between different execution modes to best adapt to the workload characteristics. In-depth evaluation with several benchmarks indicates that P8TM can achieve striking performance gains in workloads that stress the capacity limitations of HTM, while achieving performance on par with HTM even in unfavourable workloads.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1007/s00446-019-00363-1
