Design and Analysis of a 80 GHz Hybrid CMOS Dielectric Resonator Oscillator
Name
louie-tklouie-meng-eecs-2025-thesis.pdf
Description
Thesis PDF
Size
7.66 MB
Format
Adobe PDF
Checksum (MD5)
5e189a9a1ed4c54b03d3407538ff4199
Author(s)
Louie, Tiffany
Advisor(s)
Han, Ruonan
Date Issued
May 2025
Publisher
Massachusetts Institute of Technology
Abstract
This work studies a high frequency, low phase noise, hybrid CMOS oscillator based on a cylindrical dielectric resonator coupled directly to an on chip structure. Dielectric resonators (DR) are known for their high quality factor, low cost, and high temperature stability which makes them a desirable frequency selecting element in design for millimeter-wave (mmWave) applications. Current dielectric resonator oscillators (DRO) have proven to be phase stable, but are limited in frequency (< 40Ghz) due to their implementation with discrete components. However, in increasing the operational frequency up to the GHz range, it is possible to reduce size of the DR and place it directly on top of a cmos chip. We demonstrate, using a 22nm FD-SOI process, the design of a 80Ghz DRO with an area of 4mm² and an oscillator power consumption of 1.95mW. The DRO achieves a simulated phase noise of -128 dBc/Hz at 1MHz and -148 dBc/Hz at 10MHz.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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