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ASIC design and data communications for the Boston retinal prosthesis
Name
nihms784151.pdf
Description
Accepted version
Size
740.45 KB
Format
Adobe PDF
Checksum (MD5)
7eb3598e6decd18e01359e74eb185140
Author(s)
Shire, D. B.
Ellersick, W.
Kelly, S. K.
Doyle, P.
Priplata, A.
Drohan, W.
Mendoza, O.
Gingerich, M.
McKee, B.
Wyatt, J. L.
Date Issued
August 2012
Publisher
IEEE
Citation
Shire, D. B., Ellersick, W., Kelly, S. K., Doyle, P., Priplata, A. et al. 2012. "ASIC design and data communications for the Boston retinal prosthesis."
Version
Author's final manuscript
Abstract
We report on the design and testing of a custom application-specific integrated circuit (ASIC) that has been developed as a key component of the Boston retinal prosthesis. This device has been designed for patients who are blind due to age-related macular degeneration or retinitis pigmentosa. Key safety and communication features of the low-power ASIC are described, as are the highly configurable neural stimulation current waveforms that are delivered to its greater than 256 output electrodes. The ASIC was created using an 0.18 micron Si fabrication process utilizing standard 1.8 volt CMOS transistors as well as 20 volt lightly doped drain FETs. The communication system receives frequency-shift keyed inputs at 6.78 MHz from an implanted secondary coil, and transmits data back to the control unit through a lower-bandwidth channel that employs load-shift keying. The design's safety is ensured by on-board electrode voltage monitoring, stimulus charge limits, error checking of data transmitted to the implant, and comprehensive self-test and performance monitoring features. Each stimulus cycle is initiated by a transmitted word with a full 32-bit error check code. Taken together, these features allow researchers to safely and wirelessly tailor retinal stimulation and vision recovery for each patient.
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
10.1109/embc.2012.6345927
