Design and simulation of a PCI Express Gen 3.0 communication channel
Name
703295546-MIT.pdf
Description
Full printable version
Size
7.72 MB
Format
Adobe PDF
Checksum (MD5)
7bc2de158e4757947a71ba6c73cdfa8f
Author(s)
Warnakulasuriyarachchi, Dilini (Dilini M.)
Advisor(s)
Scott Westbrook and Vladimir Stojanovic.
Alternative Title
Design and simulation of a Peripheral Component Interconnect Express Gen 3.0 communication channel
Design and simulation of a PCIe Gen 3.0 communication channel
Date Issued
2010
Publisher
Massachusetts Institute of Technology
Abstract
PCI Express (PCIe) is a serial interconnect technology, developed by the PCI-Sig organization, which provides high bandwidth data transmission with the added benefits of reduced board space requirements, smaller connectors and simplified PCB layouts. Since faster and faster data rates are more desirable, PCIe Gen 3.0 attempts to transmit data at 8GT/s. As part of the thesis work, an existing model of a PCIe channel which connects two controller boards over a backplane, was simulated and measured under PCIe Gen 2.0 speeds (5GT/s). The resulting data from these tests were used to provide the basis for improving the model to make it function under PCIe Gen 3.0 specifications. This was achieved by exploring new receiver equalization techniques and transmitter de-emphasis and board characteristics. An integrated circuit manufacturer's model was used as the base model for PCIe Gen 2.0. This model was further developed to simulate Gen 3.0 speeds. Simulation software tools such as HSPICE, Ansoft HFSS, Ansoft Via Wizard 3.0 and MATLAB were utilized. A simulation model of the system functioning under PCIe Gen 3.0 specifications was successfully developed by using CTLE equalization technique.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 50-51).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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