A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction
Name
El-Moselhy-2009-A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction.pdf
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365.75 KB
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Checksum (MD5)
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Author(s)
El-Moselhy, Tarek Ali
Elfadel, Ibrahim M.
Daniel, Luca
Date Issued
December 2009
Journal
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 2009
Publisher
Institute of Electrical and Electronics Engineers
Citation
El-Moselhy, Tarek A., Ibrahim M. Elfadel, and Luca Daniel (2009). "A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction." IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 2009 (Piscataway, N.J.: IEEE): 752-758. © 2009 IEEE.
Version
Final published version
Abstract
With the adoption of ultra regular fabric paradigms for controlling design printability at the 22 nm node and beyond, there is an emerging need for a layout-driven, pattern-based parasitic extraction of alternative fabric layouts. In this paper, we propose a hierarchical floating random walk (HFRW) algorithm for computing the 3D capacitances of a large number of topologically different layout configurations that are all composed of the same layout motifs. Our algorithm is not a standard hierarchical domain decomposition extension of the well established floating random walk technique, but rather a novel algorithm that employs Markov Transition Matrices. Specifically, unlike the fast-multipole boundary element method and hierarchical domain decomposition (which use a far-field approximation to gain computational efficiency), our proposed algorithm is exact and does not rely on any tradeoff between accuracy and computational efficiency. Instead, it relies on a tradeoff between memory and computational efficiency. Since floating random walk type of algorithms have generally minimal memory requirements, such a tradeoff does not result in any practical limitations. The main practical advantage of the proposed algorithm is its ability to handle a set of layout configurations in a complexity that is basically independent of the set size. For instance, in a large 3D layout example, the capacitance calculation of 120 different configurations made of similar motifs is accomplished in the time required to solve independently just 2 configurations, i.e. a 60x speedup.
Subjects
Markov processes
boundary-elements methods
capacitance
integrated circuit layout
3D capacitance extraction
Markov transition matrices
boundary element method
hierarchical domain decomposition
hierarchical floating random walk algorithm
integrated circuit layout
parasitic extraction
size 22 nm
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5361211
