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  5. A circular pipelined bus architecture for high-speed computation

A circular pipelined bus architecture for high-speed computation

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Author(s)
Antaki, Patrick R
Advisor(s)
Stephen A. Ward.
Date Issued
1984
Publisher
Massachusetts Institute of Technology
Description
Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1984.
MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING.
Bibliography: leaves 60-61.
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.
http://dspace.mit.edu/handle/1721.1/7582
Persistent DSpace Link
http://hdl.handle.net/1721.1/109621
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