Sieve : an XML-based structural Verilog rules check tool
Name
56821844-MIT.pdf
Description
Full printable version
Size
2.68 MB
Format
Adobe PDF
Checksum (MD5)
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Author(s)
Cheng, Tina, 1980-
Advisor(s)
Krste AsanoviÄ.
Alternative Title
XML-based structural Verilog rules check tool
Date Issued
2003
Publisher
Massachusetts Institute of Technology
Abstract
The complexity of microprocessor chip designs continues to grow with every generation. At the same time, the amount of manpower needed for these projects also continues to grow, creating the need for a better integration flow. Due to this trend, many design conventions are set before the implementation of the chip commences to aid in the integration. This thesis describes the development of a suite of tools which check various design rules in accordance with predefined conventions, in particular the SCALE-0 VLSI design conventions. The tool suite consists of units that check naming conventions, units that check that the design is structural Verilog, and units that check leaf signal rules. A flexible input format for describing the rules is also developed so the tool can be easily adapted for new conventions and new chip designs. The input to the tools is a Verilog design file. Icarus Verilog is modified to parse this Verilog into an XML format. The tool then uses this format, along with the rules that have been defined, as inputs and performs the checks that are specified.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (p. 83).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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