Memory Assignment for Multiprocessor Caches Through Graph Coloring
Name
MIT-LCS-TM-465.pdf
Size
5.72 MB
Format
Adobe PDF
Checksum (MD5)
07acf2bba775f0260ae841a0a0974218
Author(s)
Agarwal, Anant
Guttag, John
Papaefthymiou, Marios
Date Issued
February 1992
Series/Report no.
MIT-LCS-TM-465
Abstract
It has become apparent that the achieved performance of multiprocessors is heavily dependent upon the quality of the availabel compilers. In this paper we are concerned with compile-time techniques that can be used to achieve better performance by improving cache utilization. Specifically, we investigate the problem of assigning data chunks to memory in a way that will minimize collisions in direct-mapped multiprocessor caches. We show that while this problem is computationally intractable, there are interesting special cases that can be solved in polynomial time. We also present several techniques that can be used when conflict-free assignment is not possible, or when finding a conflict-free assignment is computationally infeasible. These techniques include uniform decaching, which involves not caching specific data blocks, and data replication, which involves making multiple copies of read-only data. Finally, we present a memory assigment technique, grey coloring, that reduces latency in the presence of collisions by distributing cache misses among processors in a way that minimized the total number of cache misses in any specific cache.
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