Massachusetts Institute of Technology Computer Science and Artificial Intelligence Laboratory
Abstract
Digital circuits often have a critical path that runs through a smallsubset of the component subblocks, but where the path changes dynamicallyduring operation. Dynamically resizable static CMOS (DRCMOS) logic isproposed as a fine-grain leakage reduction technique that dynamicallydownsizes transistors in inactive subblocks while maintaining speed insubblocks along the current critical path. A 64-entry register free listand a 64-entry pick-two arbiter are used to evaluate DRCMOS. DRCMOS isshown to give a 50% reduction in total power for equal delay in a70 nm technology.
