A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS
Name
Liu-2009-A 10Gbs compact low-power serial IO with DFE-IIR equalization in 65nm CMOS.pdf
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776.79 KB
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Checksum (MD5)
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Author(s)
Kim, Byungsub
Dickson, Timothy O.
Liu, Yong
Bulzacchelli, John F.
Friedman, Daniel J.
Date Issued
May 2009
Journal
IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009
Publisher
Institute of Electrical and Electronics Engineers
Citation
Yong Liu et al. “A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS.” Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International. 2009. 182-183,183a. © 2009 Institute of Electrical and Electronics Engineers.
Version
Final published version
Abstract
The design of compact low-power I/O transceivers continues to be a challenge for both chip-to-chip and backplane applications. The introduction of dense fine-pitch silicon packaging technologies, that in principle are capable of supporting tens of thousands of high-data-rate I/O for local chip-to-chip interconnect, will make I/O area and power requirements even more stringent.This paper describes an alternative low-power compact I/O transceiver with RX equalization that achieves the required multi-bit postcursor cancellation without a high tap-count DFE. While this work targets data transmission over Si carrier links at rates up to 10Gb/s, it is also relevant to backplane channels.
MIT Department
Massachusetts Institute of Technology. Research Laboratory of Electronics
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/ISSCC.2009.4977368
