ATAC: A Manycore Processor with On-Chip Optical Network
Author(s)
Liu, Jifeng
Psota, James
Beckmann, Nathan
Miller, Jason
Michel, Jurgen
Eastep, Jonathan
Kurian, George
Kimerling, Lionel
Agarwal, Anant
Beals, Mark
Advisor(s)
Anant Agarwal
Date Issued
May 5, 2009
Series/Report no.
MIT-CSAIL-TR-2009-018
Abstract
Ever since industry has turned to parallelism instead of frequency scaling to improve processor performance, multicore processors have continued to scale to larger and larger numbers of cores. Some believe that multicores will have 1000 cores or more by the middle of the next decade. However, their promise of increased performance will only be reached if their inherent scaling and programming challenges are overcome. Meanwhile, recent advances in nanophotonic device manufacturing are making chip-stack optics a reality; interconnect technology which can provide significantly more bandwidth at lower power than conventional electrical analogs. Perhaps more importantly, optical interconnect also has the potential to enable new, easy-to-use programming models enabled by an inexpensive broadcast mechanism. This paper introduces ATAC, a new manycore architecture that capitalizes on the recent advances in optics to address a number of the challenges that future manycore designs will face. The new constraints and opportunities associated with on-chip optical interconnect are presented and explored in the design of ATAC. Furthermore, this paper introduces ACKwise, a novel directory-based cache coherence protocol that takes advantage of the special properties of ATAC to achieve high performance and scalability on large-scale manycores. Early performance results show that a 1000-core ATAC chip achieves a speedup of as much as 39% when compared with a similarly sized manycore with an electrical mesh network.
Subjects
Many-core processors
Processor interconnects
Optical interconnects
Persistent DSpace Link
