How to Build Scalable On-Chip ILP Networks for a Decentralized Architecture
Name
MIT-LCS-TM-628.pdf
Size
133.69 KB
Format
Adobe PDF
Checksum (MD5)
d9840bb1e0719391c185d2279bbfd5f6
Author(s)
Taylor, Michael Bedford
Lee, Walter
Frank, Matthew
Amarasinghe, Saman
Agarwal, Anant
Date Issued
April 2000
Series/Report no.
MIT-LCS-TM-628
Abstract
The era of billion transistors-on-a-chip is creating a completely different set of design constraints, forcing radically new microprocessor archiecture designs. This paper examines a few of the possible microarchitectures that are capable of obtaining scalable ILP performance. First, we observe that the network that interconnects the processing elements is the critical design point in the microarchitecture. Next, we characterize four fundamental properties that have to be satisfied by the interconnection network. Next, we provide case studies of two different networks that satisfy these properties. Finally, a detailed evaluation of these networks is presented to highlight the scalability and performance of these microarchitectures. We show that by using compile time information, we can build simpler networks and use them efficiently.
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