Energy efficient SAR ADC with resolution enhancement for sensor signals
Name
1252059453-MIT.pdf
Size
3.44 MB
Format
Adobe PDF
Checksum (MD5)
1d0cdeb57338786004e14a0996f6306f
Author(s)
Khurana, Harneet Singh.
Advisor(s)
Anantha P. Chandrakasan and Hae-Seung Lee.
Alternative Title
Energy efficient successive-approximation-register analog-to-digital converter with resolution enhancement for sensor signals
Date Issued
2021
Publisher
Massachusetts Institute of Technology
Abstract
Many signals from sensors are low activity signals that spend most of its time around middle of the full scale with occasional large activity. A/D conversion of such signals using a conventional ADC with a constant resolution and a full-scale search space consumes unnecessary amounts of time and energy. SAR ADC architecture using a comparator and Capacitor-DAC has been the choice for this application space due to minimal analog components and low static power consumption while providing moderate speed and resolution that is adequate for sensor signals. DAC and comparator power reduction has been the focus of attention as the logic automatically benefits from digital centric process scaling. This work develops an energy efficient 10B/12B SAR ADC for such sensor signals using a new algorithm to save energy and time and use the savings for resolution enhancement.
Description
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, September, February, 2021
Cataloged from the official PDF of thesis.
Includes bibliographical references (pages 129-134).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
MIT theses may be protected by copyright. Please reuse MIT thesis content according to the MIT Libraries Permissions Policy, which is available through the URL provided.
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