Reverse-engineering RLC networks with in-circuit measurement
Name
965796157-MIT.pdf
Description
Full printable version
Size
11.5 MB
Format
Adobe PDF
Checksum (MD5)
53d26ec3c6e7285fd5a788eaa801dc89
Author(s)
Gordonson, Joshua Michael
Advisor(s)
Gerald Jay Sussman.
Date Issued
2015
Publisher
Massachusetts Institute of Technology
Abstract
The hands-on side of electrical engineering is still taught using solderless breadboards. To lower the learning curve and improve the utility of solderless breadboards, I have designed and implemented a prototype that draws schematic diagrams of passive circuits that are built on a breadboard. The system reverse engineers circuits by means of a network sensing algorithm, which iteratively grounds and excites nodes with voltage sources, and subsequently measures the resulting currents and voltages in the network. Both a software simulation and a hardware implementation were built to test the network sensing algorithm. The sofware system is capable of reverse-engineering arbitrarily sized RLC networks with some caveats regarding high-q parallel RLC networks. The hardware system is able to accurately detect resistive and capacitive networks with eight nodes, though current hardware limitations significantly reduce the precision of measurment. The performance of the hardware system was analyzed and solutions to many of the measurement issues were found. A technique for surface-mount soldering breadboards to PCBs is presented in this thesis.
Description
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
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