A Probabilistic Perspective on Tiling Sparse Tensor Algebra
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3725843.3756095.pdf
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Author(s)
Sharma, Ritvik
Xue, Zi Yu
Zhang, Nathan
Lacouture, Rubens
Kjolstad, Fredrik
Achour, Sara
Horowitz, Mark
Date Issued
October 17, 2025
Publisher
ACM|58th IEEE/ACM International Symposium on Microarchitecture
Citation
Ritvik Sharma, Zi Yu Xue, Nathan Zhang, Rubens Lacouture, Fredrik Kjolstad, Sara Achour, and Mark Horowitz. 2025. A Probabilistic Perspective on
Tiling Sparse Tensor Algebra. In 58th IEEE/ACM International Symposium on
Microarchitecture (MICRO ’25), October 18–22, 2025, Seoul, Republic of Korea.
ACM, New York, NY, USA, 14 pages.
Version
Final published version
Abstract
Sparse tensor algebra computations are often memory-bound due to irregular access patterns and low arithmetic intensity. We present D2T2 (Data-Driven Tensor Tiling), a framework that optimizes static coordinate-space tiling schemes to minimize memory traffic by identifying and leveraging relevant high-level statistics from input operands. For a given tensor algebra computation, D2T2 collects statistics from input tensors, builds a probability distribution-based model of the tensor computation, and uses it to predict traffic for various tiling configurations. It searches over tile shape and size configurations to minimize total traffic. We evaluate D2T2 against Tailors and DRT, two state of the art tiling schemes for sparse tensor algebra. We find that D2T2 achieves, on average, a 2.54 × speedup over Tailors and a 1.13× lower memory bandwidth compared to DRT for sparse-sparse matrix multiplication (SpMSpM). We also achieve 1.22–48.94× lower bandwidth for SpMSpM and up to 34.31× lower bandwidth for tensor operations (TTM and MTTKRP) than conservative static tiling schemes. Unlike prior tiling techniques, D2T2 is deployable without specialized hardware support. On Opal, a 16nm sparse tensor algebra accelerator, D2T2 generated tiling configurations that achieve 1.23–3.34 × speedups compared to their original hand-tuned configurations.
Description
MICRO ’25, Seoul, Republic of Korea
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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DOI of Published Version
https://doi.org/10.1145/3725843.3756095
