A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs
Name
RC-261 paper.pdf
Description
Accepted version
Size
1.93 MB
Format
Adobe PDF
Checksum (MD5)
903eb558df0262b734516c3a32806434
Author(s)
Vardi, Assaf
Lin, Jian
Lu, W.
Zhao, X.
Fernando Saavedra, Amalia Luisa
del Alamo, Jesus A
Date Issued
November 2017
Journal
IEEE Transactions on Semiconductor Manufacturing
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Vardi, A. et al. "A Si Compatible Fabriacaton Process for Scaled Self-Aligned InGaAs FinFets." IEEE Transactions on Semiconductor Manufacturing, 30, 4 (November 2017): 468 - 474 © 2017 IEEE
Version
Author's final manuscript
Abstract
We have developed a scalable gate-last process to fabricate self-aligned InGaAs FinFETs that relies on extensive use of dry etch. The process involves F-based dry etching of refractory metal ohmic contacts that are formed early in the process. The fins are etched in a novel inductive coupled plasma process using BCl[subscript 3]/SiCl[subscript 4]/Ar. High aspect ratio fins with smooth sidewalls are obtained. To further improve the quality of the sidewalls and shrink the fin width, digital etch is used. Through this process flow, we have demonstrated FinFETs with L[subscript g] = 20 nm and fin width as narrow as 7 nm with high yield. Good electrostatic characteristics are obtained in a wide range of device dimensions. In devices with 7 nm fin width, record channel aspect ratio, and transconductance per unit footprint are obtained.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1109/tsm.2017.2753141
