Memory coherence in the age of multicores
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Devadas-Memory coherence.pdf
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241.44 KB
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Author(s)
Lis, Mieszko
Shim, Keun Sup
Cho, Myong Hyon
Devadas, Srinivas
Date Issued
November 2011
Journal
IEEE 29th International Conference on Computer Design 2011 (ICCD)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Lis, Mieszko et al. “Memory Coherence in the Age of Multicores.” IEEE 29th International Conference on Computer Design 2011 (ICCD). 1–8.
Version
Author's final manuscript
Abstract
As we enter an era of exascale multicores, the question of efficiently supporting a shared memory model has become of paramount importance. On the one hand, programmers demand the convenience of coherent shared memory; on the other, growing core counts place higher demands on the memory subsystem and increasing on-chip distances mean that interconnect delays are becoming a significant part of memory access latencies. In this article, we first review the traditional techniques for providing a shared memory abstraction at the hardware level in multicore systems. We describe two new schemes that guarantee coherent shared memory without the complexity and overheads of a cache coherence protocol, namely execution migration and library cache coherence. We compare these approaches using an analytical model based on average memory latency, and give intuition for the strengths and weaknesses of each. Finally, we describe hybrid schemes that combine the strengths of different schemes.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike 3.0
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DOI of Published Version
https://doi.org/10.1109/ICCD.2011.6081367
