Unveiling the carrier transport mechanism in epitaxial graphene for forming wafer-scale, single-domain graphene
Name
Bae-2017-Unveiling the carrier transport mecha.pdf
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Author(s)
Zhou, Xiaodong
Kim, Seyoung
Lee, Yun Seog
Hannon, James B.
Yang, Yang
Sadana, Devendra K.
Ross, Frances M.
Park, Hongsik
Bae, Sanghoon
Cruz, Samuel Steven
Date Issued
April 2017
Journal
Proceedings of the National Academy of Sciences
Publisher
Proceedings of the National Academy of Sciences
Citation
Bae, Sang-Hoon, et al. “Unveiling the Carrier Transport Mechanism in Epitaxial Graphene for Forming Wafer-Scale, Single-Domain Graphene.” Proceedings of the National Academy of Sciences, vol. 114, no. 16, Apr. 2017, pp. 4082–86. © 2017 National Academy of Sciences
Version
Final published version
Abstract
Graphene epitaxy on the Si face of a SiC wafer offers monolayer graphene with unique crystal orientation at the wafer-scale. However, due to carrier scattering near vicinal steps and excess bilayer stripes, the size of electrically uniform domains is limited to the width of the terraces extending up to a few microns. Nevertheless, the origin of carrier scattering at the SiC vicinal steps has not been clarified so far. A layer-resolved graphene transfer (LRGT) technique enables exfoliation of the epitaxial graphene formed on SiC wafers and transfer to flat Si wafers, which prepares crystallographically single-crystalline monolayer graphene. Because the LRGT flattens the deformed graphene at the terrace edges and permits an access to the graphene formed at the side wall of vicinal steps, components that affect the mobility of graphene formed near the vicinal steps of SiC could be individually investigated. Here, we reveal that the graphene formed at the side walls of step edges is pristine, and scattering near the steps is mainly attributed by the deformation of graphene at step edges of vicinalized SiC while partially from stripes of bilayer graphene. This study suggests that the two-step LRGT can prepare electrically single-domain graphene at the wafer-scale by removing the major possible sources of electrical degradation.
MIT Department
Massachusetts Institute of Technology. Department of Materials Science and Engineering
Massachusetts Institute of Technology. Department of Mechanical Engineering
Massachusetts Institute of Technology. Research Laboratory of Electronics
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DOI of Published Version
https://doi.org/10.1073/PNAS.1620176114
