Quantum capacitance in scaled down III-V FETs
Name
Donghyun-2009-Quantum capacitance in scaled down III-V FETs.pdf
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Author(s)
Jin, Donghyun
Kim, Dae-Hyun
Kim, Tae-Woo
del Alamo, Jesus A.
Date Issued
March 2010
Journal
2009 IEEE International Electron Devices Meeting (IEDM)
Publisher
Institute of Electrical and Electronics Engineers
Citation
Donghyun Jin et al. “Quantum capacitance in scaled down III–V FETs.” Electron Devices Meeting (IEDM), 2009 IEEE International. 2009. 1-4. © Copyright 2010 IEEE
Version
Final published version
Abstract
We have built a physical gate capacitance model for III-V FETs that incorporates quantum capacitance and centroid capacitance in the channel. We verified its validity with simulations (Nextnano) and experimental measurements on High Electron Mobility Transistors (HEMTs) with InAs and InGaAs channels down to 30 nm in gate length. Our model confirms that in the operational range of these devices, the quantum capacitance significantly lowers the overall gate capacitance. In addition, the channel centroid capacitance is also found to have a significant impact on gate capacitance. Our model provides a number of suggestions for capacitance scaling in future III-V FETs.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology. Microsystems Technology Laboratories
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/IEDM.2009.5424312
