Modular Deductive Verification of Multiprocessor Hardware Designs
Name
BlueCAV15.pdf
Description
Accepted version
Size
375.98 KB
Format
Adobe PDF
Checksum (MD5)
4b63aa2f14f4a106dd9e9bc7c0f56734
Author(s)
Vijayaraghavan, Muralidaran
Chlipala, Adam
Arvind, Arvind
Nirav, Dave
Date Issued
July 2015
Journal
CAV 2015: Computer Aided Verification
Publisher
Springer International Publishing
Citation
Vijayaraghavan, Muralidaran et al. "Modular Deductive Verification of Multiprocessor Hardware Designs." CAV 2015: Computer Aided Verification (July 2015): 109-127 © 2015 Springer International Publishing Switzerland
Version
Author's final manuscript
Abstract
We present a new framework for modular verification of hardware designs in the style of the Bluespec language. That is, we formalize the idea of components in a hardware design, with well-defined input and output channels; and we show how to specify and verify components individually, with machine-checked proofs in the Coq proof assistant. As a demonstration, we verify a fairly realistic implementation of a multicore shared-memory system with two types of components: memory system and processor. Both components include nontrivial optimizations, with the memory system employing an arbitrary hierarchy of cache nodes that communicate with each other concurrently, and with the processor doing speculative execution of many concurrent read operations. Nonetheless, we prove that the combined system implements sequential consistency. To our knowledge, our memory-system proof is the first machine verification of a cache-coherence protocol parameterized over an arbitrary cache hierarchy, and our full-system proof is the first machine verification of sequential consistency for a multicore hardware design that includes caches and speculative processors. Keywords: Hardware Design; Label Transition System; Speculative Load; Program Counter; Coherence State
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1007/978-3-319-21668-3_7
