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  4. Improving the Systems Engineering Process with Multilevel Analysis of Interactions

Improving the Systems Engineering Process with Multilevel Analysis of Interactions

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Author(s)
Eppinger, Steven D.
•
Joglekar, Nitin R.
•
Olechowski, Alison L.
•
Teo, Terence
Date Issued
March 2014
Publisher
Massachusetts Institute of Technology. Engineering Systems Division
Series/Report no.
ESD Working Papers;ESD-WP-2014-02
Abstract
The systems engineering V (SE-V) is an established process model to guide the development of complex engineering projects (INCOSE, 2011). The SE-V process involves decomposition and integration of system elements through a sequence of tasks that produce both a system design and its testing specifications, followed by successive levels of build, integration, and test activities. This paper presents a method to improve SE-V implementation by mapping multilevel data into design structure matrix (DSM) models. DSM is a representation methodology for identifying interactions either between components or tasks associated with a complex engineering project (Eppinger & Browning, 2012). Multilevel refers to SE-V data on complex interactions that are germane either at multiple levels of analysis, e.g. component versus subsystem conducted either within a single phase or across multiple time phases, e.g. early or late in the SE-V process. This method extends conventional DSM representation schema by incorporating multilevel test coverage data as vectors into the off diagonal cells. These vectors provide a richer description of potential interactions between product architecture and SE-V integration test tasks than conventional domain mapping matrices (DMMs). We illustrate this method with data from a complex engineering project in the offshore oil industry. Data analysis identifies potential for unanticipated outcomes based on incomplete coverage of SE-V interactions during integration tests. Additionally, assessment of multilevel features using maximum and minimum function queries isolates all the interfaces that are associated with either early or late revelations of integration risks based on the planned suite of SE-V integration tests.
Persistent DSpace Link
http://hdl.handle.net/1721.1/102988
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