A fractionally spaced linear receive equalizer with voltage-to-time conversion
Name
Stojanovic_A Fractionally.pdf
Size
182.12 KB
Format
Adobe PDF
Checksum (MD5)
8252832b5a8910fa0e9dcf7f6b4a68d9
Author(s)
Stojanovic, Vladimir Marko
Song, Sanquan
Kim, Byungsub
Date Issued
August 2009
Journal
2009 Symposium on VLSI Circuits, Digest of Technical Papers
Publisher
Institute of Electrical and Electronics Engineers
Citation
Song, Sanquan, Byungsub Kim, and Vladimir Stojanovic. “A fractionally spaced linear receive equalizer with voltage-to-time conversion.” VLSI Circuits, 2009 Symposium on. 2009. 222-223. ©2009 IEEE.
Version
Author's final manuscript
Abstract
Based on voltage-to-time conversion technique, a pseudo-differential two-way-interleaved adaptive linear receive equalizer with two 2x-oversampled feed-forward taps has been designed in a 90 nm CMOS process. It integrates equalization and phase interpolation functions into one unit to simultaneously address inter-symbol-interference (ISI) cancellation and phase synchronization in a link receiver. It operates at 4 Gbps with 8 mW power consumption, and linearity of 4.3 effective bits at 1.2 V supply.
Description
link to article page on IEEE
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Attribution-Noncommercial-Share Alike 3.0 Unported
Persistent DSpace Link
DOI of Published Version
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5205338
