New Lower Bound Techniques For VLSI
Name
MIT-LCS-TM-227.pdf
Size
7.46 MB
Format
Adobe PDF
Checksum (MD5)
f6c4e263b20f5e152e9f4a933d40fcb9
Author(s)
Leighton, Frank Thomson
Date Issued
August 1982
Series/Report no.
MIT-LCS-TM-227
Abstract
In this paper, we use crossing number and wire area arguments to find lower bounds on the layout area and maximum edge length of a variety of new and computationally useful networks. In particular, we describe 1) an N-node planar graph which has layout area ⊖ (NlogN) and maximum edge length ⊖(N^1/2/log^1/2N), 2) an N-node graph with an O(x^1/2)-separator which has layout area ⊖ (Nlog^2N) and maximum edge length ⊖ (N^1/2logN/loglogN), and 3) an N-node graph with an O(x^1-1/r)-separator which has maximum edge length ⊖(N1-1/4) for an r≥3.
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