Full utilization, fairness, and access delay on high speed slotted bus networks
Name
36598377-MIT.pdf
Description
Full printable version
Size
4.41 MB
Format
Adobe PDF
Checksum (MD5)
bfd05c8aa965a778d446c8f6145528bc
Author(s)
Chiu, Angela Lan
Date Issued
1997
Publisher
Massachusetts Institute of Technology, Laboratory for Information and Decision Systems
Massachusetts Institute of Technology
Series/Report no.
LIDS-P ; 2382.
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.
Includes bibliographical references (p. 89-92).
Subjects
Laboratory for Information and Decision Systems.
MIT Department
Massachusetts Institute of Technology. Laboratory for Information and Decision Systems
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
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