Functional and timing models for a programmable hardware accelerator
Name
932129075-MIT.pdf
Description
Full printable version
Size
1.77 MB
Format
Adobe PDF
Checksum (MD5)
64a9f150454593e366fdfa5b6bf08a40
Author(s)
Fox, Matthew (Matthew M.)
Advisor(s)
Joel Emer and Vivienne Sze.
Date Issued
2015
Publisher
Massachusetts Institute of Technology
Abstract
Classes of problems that exhibit high levels of data reuse have heavy overhead costs due to the necessity of repeated memory accesses. A proposed programmable hardware accelerator using a spatial architecture paired with triggered instructions could solve this class of problems more efficiently. Performance models are useful for evaluating the performance of different applications and design alternatives. This project develops a functional model for this hardware accelerator as well as a simple timing model to allow for examination of the performance of this proposed architecture. Furthermore, convolution, pooling, and non-linearity are implemented as programs on this accelerator in order to show functionality and flexibility present within the system. This project shows the feasibility of a spatial architecture powered by triggered instructions and provides the framework for future testing and prototyping for this problem space.
Description
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (page 79).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
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