Stochastic In-memory Computing Using Magnetic Tunnel Junctions
Name
wang-qiuyuan-sm-eecs-2024-thesis.pdf
Description
Thesis PDF
Size
4.25 MB
Format
Adobe PDF
Checksum (MD5)
048ceba345c48c3b6f9f35aca4215e99
Author(s)
Wang, Qiuyuan
Advisor(s)
Liu, Luqiao
Date Issued
May 2024
Publisher
Massachusetts Institute of Technology
Abstract
Current computing hardware based on von Neumann architecture and digital CMOS circuits face strong challenges to further scale up for big AI models and data-centric applications. However, while being actively studied, it is still not clear which alternative computing paradigm is the best solution considering the fabrication maturity, scalability, operation conditions, cost, power/area efficiency, and so on. In this thesis, we propose a new alternative computing framework – stochastic in-memory computing using magnetic tunnel junctions. By introducing thermally stable and unstable magnetic tunnel junctions as CMOS-compatible circuit building blocks, both general-purpose and application-specific in-memory computing accelerators can be synthesized, providing a versatile and very high-efficiency hardware design framework for multiple applications. A deep learning accelerator is implemented and benchmarked on FPGA following the proposed stochastic in-memory computing architecture, with stochastic bitstreams sampled from thermally unstable magnetic tunnel junction fabricated in lab. The hardware designs for a Bayesian inference accelerator and Ising machine are also provided. Our results show magnetic tunnel junctions could open up rich design space for future computing hardware.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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