A modeling and exploration framework for interconnect network design in the nanometer Era
Name
Joshi-2009-A modeling and exploration framework for interconnect network design in the nanometer Era.pdf
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Author(s)
Stojanovic, Vladimir Marko
Chen, Fred Fu-Chin
Joshi, Ajay J.
Date Issued
June 2009
Journal
Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip (NoCS 2009)
Publisher
Institute of Electrical and Electronics Engineers
Citation
Joshi, A., F. Chen, and V. Stojanovic. “A Modeling and exploration framework for interconnect network design in the nanometer era.” Networks-on-Chip, 2009. NoCS 2009. 3rd ACM/IEEE International Symposium on. 2009. 91. © 2009 IEEE
Version
Final published version
Abstract
As we approach serious scaling roadblocks in the next few process nodes, it is imperative to identify new emerging technologies that can complement or supplant CMOS in the future. We present an integrated cyclic approach to explore new interconnect technologies in the nanometer era for many core systems, where on-chip interconnects are jointly optimized at all the levels in the design hierarchy to develop a complete interconnect solution - from interconnect technology to network topology.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
http://dx.doi.org/10.1109/NOCS.2009.5071454
