Simulation Modelling of Silicon Gated Field Emitter Based Electronic Circuits
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applsci-13-12807.pdf
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2.97 MB
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Checksum (MD5)
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Author(s)
Hay, Robert
Bhattacharya, Ranajoy
Chern, Winston
Rughoobur, Girish
Akinwande, Akintunde I.
Browning, Jim
Date Issued
November 29, 2023
Publisher
Multidisciplinary Digital Publishing Institute
Citation
Applied Sciences 13 (23): 12807 (2023)
Version
Final published version
Abstract
Vacuum transistors (VTs) are promising candidates in electronics due to their fast response and ability to function in harsh environments. In this study, several oscillator and logic gate circuit simulations using VTs are demonstrated. Silicon-gated field emitter arrays (Si-GFEAs) with 1000 × 1000 arrays were used experimentally to create a VT model. First, transfer and output characteristics sweeps were measured, and based on those data, an LTspice vacuum transistor (VT) model was developed. Then, the model was used to develop Wein and Ring oscillator circuits. The circuits were analytically simulated using LTspice, where the collector bias voltage was 200 V DC, and the gate bias voltage was 30–40 V DC. The Wein oscillator circuit produced a frequency of 102 kHz with a magnitude of 26 Vpp. The Ring oscillator produced a frequency of 1.14 MHz with a magnitude of 4 Vpp. Furthermore, two logic circuits, NOR and NAND gates, were also demonstrated using LTspice modeling. These simulation results illustrate the feasibility of integrating VTs into functional integrated circuits and provide a design approach for future on-chip vacuum transistors applied in logic or radio-frequency (RF) devices.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution
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DOI of Published Version
https://doi.org/10.3390/app132312807
