A study of through-silicon-via (TSV) induced transistor variation
Name
756464880-MIT.pdf
Description
Full printable version
Size
10.28 MB
Format
Adobe PDF
Checksum (MD5)
2a77c80cc1b32f9e2994d91211dc69f7
Author(s)
Yu, Li, S.M. Massachusetts Institute of Technology
Advisor(s)
Duane S. Boning.
Alternative Title
Study of through-silicon-vias (TSVs) induced transistor variation
Date Issued
2011
Publisher
Massachusetts Institute of Technology
Abstract
As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidth and power efficiency. Through-siliconvias (TSVs), which directly connect stacked structures die-to-die, is one of the key techniques enabling 3D integration. The process steps and physical presence of TSVs, however, may generate a stress-induced thermal mismatch between TSVs and the silicon bulk. These effects could further perturb the performance of nearby electronic structures, particularly transistors, diodes, and associated circuits. This thesis presents a comprehensive study to characterize, analyze and model the impact of TSV-induced stress impact on device and circuit performance and its interaction with polysilicon and shallow-trench-isolation (STI) layout pattern density. A test chip is designed with multiplexing test circuits providing measurements of key parameters of a large number of devices. These devices under test (DUTs) have layouts that explore a range of TSV and device layout choices in the design of experiments (DOEs). The test chip uses a scan chain approach combined with low-leakage and low-variation switches and Kelvin sensing connections, which provide access to detailed analog device characteristics in large arrays of test devices. A test circuit and an Ioff measurement method is designed to perform off-chip wafer probe testing measurement. In addition, a finite element analysis model is constructed to mimic realistic TSV structures and processes. A complete flow and methodology to analyze transistor characteristics and circuit performance under the influence of TSV stress is proposed. An efficient algorithm is also proposed to simulate full-chip circuit variation under the impact of TSV stress based on a grid partition approach. Test cases corresponding to the aforementioned test chip are simulated for comparison with measurement data.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 83-85).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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