Improving wafer-scale Josephson junction resistance variation in superconducting quantum coherent circuits
Name
1909.09165.pdf
Description
Accepted version
Size
4.05 MB
Format
Adobe PDF
Checksum (MD5)
df84abd9e7a15871771c8b4c8a7b2b2a
Author(s)
Kreikebaum, J M
O'Brien, Kevin
Morvan, A
Siddiqi, I
Date Issued
May 2020
Journal
Superconductor Science and Technology
Publisher
IOP Publishing
Citation
Kreikebaum, J. M. et al. "Improving wafer-scale Josephson junction resistance variation in superconducting quantum coherent circuits." 33, 6 (May 2020): 06LT02. © 2020 The Author(s)
Version
Author's final manuscript
Abstract
Quantum bits, or qubits, are an example of coherent circuits envisioned for next-generation computers and detectors. A robust superconducting qubit with a coherent lifetime of O(100 µs) is the transmon: a Josephson junction functioning as a non-linear inductor shunted with a capacitor to form an anharmonic oscillator. In a complex device with many such transmons, precise control over each qubit frequency is often required, and thus variations of the junction area and tunnel barrier thickness must be sufficiently minimized to achieve optimal performance while avoiding spectral overlap between neighboring circuits. Simply transplanting our recipe optimized for single, stand-alone devices to wafer-scale (producing 64, 1x1 cm dies from a 150 mm wafer) initially resulted in global drifts in room-temperature tunneling resistance of 30%. Inferring a critical current ≡σIc≪Ic≫ variation from this resistance distribution, we present an optimized process developed from a systematic 38 wafer study that results in < 3.5% relative standard deviation (RSD) in critical current () for 3000 Josephson junctions (both single-junctions and asymmetric SQUIDs) across an area of 49 cm2. Looking within a 1x1 cm moving window across the substrate gives an estimate of the variation characteristic of a given qubit chip. Our best process, utilizing ultrasonically assisted development, uniform ashing, and dynamic oxidation has shown = 1.8% within 1x1 cm, on average, with a few 1x1 cm areas having < 1.0% (equivalent to < 0.5%). Such stability would drastically improve the yield of multi-junction chips with strict critical current requirements.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1088/1361-6668/ab8617
