The Other Face of On-Chip Interconnect
Name
Agrawal-2009-The other face of on-chip interconnect.pdf
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51.45 KB
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Adobe PDF
Checksum (MD5)
6712694bfa518f3259d45138560d45a8
Author(s)
Agarwal, Anant
Date Issued
September 2009
Journal
Proceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009. HOTI 2009.
Publisher
Institute of Electrical and Electronics Engineers
Citation
Agarwal, A. "Keynote: The Other Face of On-Chip Interconnect," in Proceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009. HOTI 2009. pp.xii-xii, 25-27 Aug. 2009. ©2009 Institute of Electrical and Electronics Engineers.
Version
Final published version
Abstract
The multicore revolution has changed the way we think about computing. The same movement has also changed the way we look at on-chip interconnect because it is a key determinant of the performance and power efficiency of multicores. This talk will highlight some of the lesser known issues and opportunities of on-chip interconnect, such as protection, programming ease, and the impact on the basic structure of our software. The talk will borrow heavily from our experiences with on-chip interconnect in university research with the 16-core Raw multicore processor, in a commercial environment with Tilera's 64-core Tile processor, and in a future 1K-core multicore processor called ATAC that integrates optical and electrical interconnects.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
Persistent DSpace Link
DOI of Published Version
http://dx.doi.org/10.1109/HOTI.2009.28
