Investigation of hole mobility in gate-all-around Si nanowire p-MOSFETs with high-k/metal-gate: Effects of hydrogen thermal annealing and nanowire shape
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Hoyt_Investigation of hole.pdf
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1.27 MB
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Author(s)
Hashemi, Pouya
Teherani, James T.
Hoyt, Judy L.
Date Issued
January 2011
Journal
2010 IEEE International Electron Devices Meeting (IEDM)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Hashemi, Pouya, James T. Teherani, and Judy L. Hoyt. “Investigation of Hole Mobility in Gate-all-around Si Nanowire p-MOSFETs with high-к/metal-gate: Effects of Hydrogen Thermal Annealing and Nanowire Shape.” IEEE, 2010. 34.5.1–34.5.4. © Copyright 2010 IEEE
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Final published version
Abstract
A detailed study of hole mobility is presented for gate-all-around Si nanowire p-MOSFETs with conformal high-κ/MG and various high-temperature hydrogen annealing processes. Hole mobility enhancement relative to planar SOI devices and universal (100) is observed for 15 nm-diameter circular Si nanowires, due to an optimized anneal process which smoothes and reshapes the suspended nanowires. Increasing hole mobility is experimentally observed with decreasing nanowire width down to 12 nm. The measured inversion capacitance-voltage characteristics are in excellent agreement with quantum mechanical simulations. In addition, a method to extract areal inversion charge density in Si nanowires is introduced and its impact on the mobility of Si nanowires with various shapes is explored.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology. Microsystems Technology Laboratories
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/IEDM.2010.5703477
