Dribble-Back Registers: A Technique for Latency Tolerance in Multiprocessors
Name
MIT-LCS-TM-474.pdf
Size
1.54 MB
Format
Adobe PDF
Checksum (MD5)
ceeee1c210fee11d80edad8f7977e4a4
Author(s)
Soundararajan, Vijayaraghavan
Advisor(s)
Agarwal, Anant
Date Issued
June 1992
Series/Report no.
MIT-LCS-TM-474
Abstract
As parallel machines grow in scale and complexity, latency tolerance of synchronization faults and remote memory accesses becomes increasingly important. One method for tolerating this by multithreading the processor and rapidly context switching between these threads. Fast context switching is most effective when the latencies being tolerated are short compared to the total run lengths of all the resident threads.
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