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The AEGIS Processor Architecture for Tamper-Evident and Tamper-Resistant Processing
Name
MIT-LCS-TR-883b.pdf
Size
369.99 KB
Format
Adobe PDF
Checksum (MD5)
aa5ecbc645a4e731e0fd29a1948d6993
Author(s)
Suh, G. Edward
Clarke, Dwaine
Gassend, Blaise
van Dijk, Marten
Devadas, Srinivas
Date Issued
2003
Series/Report no.
MIT-LCS-TR-883b
Abstract
We describe the architecture of the AEGIS processor which can be used to build computing systems secure against both physical and software attacks. AEGIS assumes that the operating system and all components external to it, such as memory, are untrusted. AEGIS provides tamper-evident, authenticated environments in which any physical or software tampering by the adversary is guaranteed to be detected, and private and authenticated, tamper-resistant environments where additionally the adversary is unable to obtain any information about software or data by tampering with, or otherwise observing, system operation. AEGIS enables many applications, such as commercial grid computing, software licensing, and digital rights management. We present a new encryption/decryption method that successfully hides a significant portion of encryption/decryption latency, in comparison to a conventional direct encryption scheme. Efficient memory encryption and integrity verification enable the implementation of a secure computing system with the only trusted component being a single-chip AEGIS CPU. Detailed simulation results indicate that the performance overhead of security mechanisms in AEGIS is reasonable.
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