Degradation of vertical GaN-on-GaN fin transistors: Step-stress and constant voltage experiments
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1-s2.0-S0026271418304608-main.pdf
Description
Published version
Size
1.61 MB
Format
Adobe PDF
Checksum (MD5)
35e21d09071a7095b60b10b69ded198d
Author(s)
Ruzzarin, M.
Meneghini, M.
De Santi, C.
Sun, Min
Palacios, Tomas
Meneghesso, G.
Zanoni, E.
Date Issued
September 2018
Journal
Microelectronics Reliability
Publisher
Elsevier BV
Citation
Ruzzarin, M. et al. "Degradation of vertical GaN-on-GaN fin transistors: Step-stress and constant voltage experiments." Microelectronics Reliability 88-90 (September 2018): 620-626 © 2018 The Authors
Version
Final published version
Abstract
We present an extensive analysis of the degradation of GaN-on-GaN fin-vertical transistors submitted to stress under positive gate voltage and off-state conditions. By analysing the degradation kinetics we demonstrate the existence of different processes: (i) trapping of electrons in the gate insulator under positive gate bias, (ii) time-dependent breakdown of the gate MOS structure under forward gate voltage; (iii) catastrophic failure for off-state voltages higher than 280 V. 2D simulations are used to identify the physical location of the failed region, and to investigate the dependence of electric field on fin width (values between 70 nm, 195 nm and 280 nm). Keywords: Vertical transistors; GaN; Stability; Degradation; Reliability
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Creative Commons Attribution-NonCommercial-NoDerivs License
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1016/j.microrel.2018.06.044
