High-level synthesis of pipelined circuits from modular queue-based specifications
Name
ieice01.pdf
Description
Published version
Size
278.54 KB
Format
Adobe PDF
Checksum (MD5)
85bd122b4c9a556a12063ed7160d3b70
Author(s)
Marinescu, MC
Rinard, M
Date Issued
January 1, 2001
Journal
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Citation
Marinescu, MC and Rinard, M. 2001. "High-level synthesis of pipelined circuits from modular queue-based specifications." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E84-A (11).
Version
Author's final manuscript
Abstract
This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modular specification language with an efficient implementation. In our system, the designer specifies the circuit as a set of independent modules connected by conceptually unbounded queues. Our synthesis algorithm automatically transforms this modular, asynchronous specification into a tightly coupled, fully synchronous implementation in synthesizable Verilog.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Terms of Use
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