Allocating decoupling capacitors to reduce simultaneous switching noise on chips
Name
56985448-MIT.pdf
Description
Full printable version
Size
7.04 MB
Format
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Checksum (MD5)
77dae7fddc28af5e8756974f6ff769f1
Author(s)
Granich Unikowsky, Adam, 1981-
Advisor(s)
Paul Stabler and Christopher J. Terman.
Date Issued
2004
Publisher
Massachusetts Institute of Technology
Abstract
L dI/dt noise due to simultaneous switching of circuits on chips is a growing problem in VLSI design. This kind of noise can lead to timing errors and significant circuit slowdowns, if not kept within reasonable bounds. The most common way of reducing this form of noise is the addition of decoupling capacitance on chip. However, adding decoupling capacitance can take significant area and can make routing very difficult. The goals of this thesis are twofold: first, to characterize the relationship between noise propagation on chip and parameters such as on-chip resistance and capacitance; and second, to develop an algorithm which will minimize the number of decoupling capacitors on chip while simultaneously reducing the noise to within acceptable boundaries.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (leaves 108-110).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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