Simulation of a novel multiprocessor system based on dataflow principles
Name
965197436-MIT.pdf
Description
Full printable version
Size
2.58 MB
Format
Adobe PDF
Checksum (MD5)
750305dbe4258479f9ebe89e77581721
Author(s)
Zhou, Mo, S.M. Massachusetts Institute of Technology
Advisor(s)
Jack B. Dennis.
Date Issued
2016
Publisher
Massachusetts Institute of Technology
Abstract
This thesis research is a study of a novel processor architecture for a massively parallel computer system. An existing simulation of the Fresh Breeze architecture has been extended to incorporate a multi-level memory hierarchy and dynamic load balancing. An efficient hardware-based garbage collection mechanism has been proposed. Various design trade-offs are evaluated. The simulation demonstrates that the architecture can support memory access with DRAM latency and still achieve high processor utilization.
Description
Thesis: S.M. in Computer Science and Engineering, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 53-54).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
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