Highly Scaled p-GaN-gate HEMTs for Low Voltage Power Electronics
Name
darmawiiskandar-pdi-sm-eecs-2025-thesis.pdf
Description
Thesis PDF
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5.3 MB
Format
Adobe PDF
Checksum (MD5)
e1fc55305c4ef309f09c16af1f270e38
Author(s)
Darmawi-Iskandar, Patrick
Advisor(s)
Palacios, Tomás
Date Issued
May 2025
Publisher
Massachusetts Institute of Technology
Abstract
Rising global energy demands, driven by the advent of artificial intelligence (AI), cloud computing, and Internet of Things (IoT) devices, underscore the need for more efficient power electronics. In particular, power switches based on wide bandgap semiconductors such as gallium nitride (GaN) have emerged as promising alternatives to traditional silicon devices for low-voltage (10-100 V) applications. This work investigates the design, fabrication, and scaling of p-GaN-gate highelectron-mobility transistors (HEMTs). A p-GaN-gate epitaxial structure was developed with considerations for short channel effects. A self-aligned, gate-first process employing tungsten metallization was implemented to enable gate lengths as small as 100 nm. Device scaling was studied systematically, revealing the importance of gate aspect ratio and gate-to-drain spacing in managing short channel effects and maintaining breakdown voltage. Electrical characterization showed strong device performance, although contact resistance accounted for a substantial portion of total on-resistance. To address this, a modified fabrication approach incorporating regrown contacts was introduced, resulting in reduced contact resistance and improved overall device characteristics. The combined results highlight practical strategies for enhancing the performance and scalability of p-GaN-gate HEMTs for next-generation low-voltage power electronics.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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