Nanofabrication of arrays of silicon field emitters with vertical silicon nanowire current limiters and self-aligned gates
Name
Nanofabrication of arrays.pdf
Size
2.55 MB
Format
Adobe PDF
Checksum (MD5)
1086c3568085deff6c97221fbbb549ab
Author(s)
Guerrera, Stephen
Akinwande, Akintunde I
Date Issued
June 2016
Journal
Nanotechnology
Publisher
IOP Publishing
Citation
Guerrera, S A and Akinwande, A I. “Nanofabrication of Arrays of Silicon Field Emitters with Vertical Silicon Nanowire Current Limiters and Self-Aligned Gates.” Nanotechnology 27, 29 (June 2016): 295302 © 2016 IOP Publishing Ltd
Version
Final published version
Abstract
We developed a fabrication process for embedding a dense array (10⁸cm⁻²) of high-aspect-ratio silicon nanowires (200 nm diameter and 10 μm tall) in a dielectric matrix and then structured/exposed the tips of the nanowires to form self-aligned gate field emitter arrays using chemical mechanical polishing (CMP). Using this structure, we demonstrated a high current density (100 A cm⁻²), uniform, and long lifetime (>100 h) silicon field emitter array architecture in which the current emitted by each tip is regulated by the silicon nanowire current limiter connected in series with the tip. Using the current voltage characteristics and with the aid of numerical device models, we estimated the tip radius of our field emission arrays to be ≈4.8 nm, as consistent with the tip radius measured using a scanning electron microscope (SEM).
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology. Microsystems Technology Laboratories
Terms of Use
Creative Commons Attribution 3.0 Unported license
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1088/0957-4484/27/29/295302
