Modeling defect-level switching for nonlinear and hysteretic electronic devices
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224501_1_5.0197121.pdf
Description
Published version
Size
2.19 MB
Format
Adobe PDF
Checksum (MD5)
fd32846ad5b8cfe4d1998269ced4fc24
Author(s)
Dong, Jiahao
Jaramillo, R
Date Issued
June 10, 2024
Journal
Journal of Applied Physics
Publisher
AIP Publishing
Citation
Jiahao Dong, R. Jaramillo; Modeling defect-level switching for nonlinear and hysteretic electronic devices. J. Appl. Phys. 14 June 2024; 135 (22): 224501
Version
Final published version
Abstract
Previously, we demonstrated hysteretic and persistent changes of resistivity in two-terminal electronic devices based on charge trapping and detrapping at immobile metastable defects [Yin et al., Phys. Rev. Appl. 15, 014014 (2021)]; we termed these defect-level switching (DLS) devices. DLS devices feature all-electronic resistive switching and thus are volatile because of the “voltage-time” dilemma. However, the dynamics of volatile resistive switches may be valuable for emerging applications such as selectors in crosspoint memory and neuromorphic computing concepts. To design circuits using these volatile resistive switches, accurate modeling is essential. In this work, we develop an accurate and analytical model to describe the switching in DLS devices, based on the established theories of point defect metastability in Cu(In,Ga)Se2 (CIGS) and II–VI semiconductors. The analytical nature of our model allows for time-efficient simulations of dynamical behavior of DLS devices. We model the time durations of SET and RESET programming pulses, which can be exponentially shortened with respect to the pulse amplitude. We also demonstrate the concept of inverse design: given desired resistance states, the width and amplitude of the programming signal can be chosen accordingly.
MIT Department
Massachusetts Institute of Technology. Department of Materials Science and Engineering
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Creative Commons Attribution
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DOI of Published Version
https://doi.org/10.1063/5.0197121
