A 0.077 to 0.168 nJ/bit/iteration Scalable 3GPP LTE Turbo Decoder with an Adaptive Sub-Block Parallel Scheme and an Embedded DVFS Engine
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Chandrakasan-a 0.077 to 0.168.pdf
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210.31 KB
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Author(s)
Cheng, Chih-Chi
Tsai, Yi-Min
Chen, Liang-Gee
Chandrakasan, Anantha P.
Date Issued
September 2010
Journal
2010 IEEE Custom Integrated Circuits Conference (CICC)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Chih-Chi Cheng et al. “A 0.077 to 0.168 nJ/bit/iteration Scalable 3GPP LTE Turbo Decoder with an Adaptive Sub-block Parallel Scheme and an Embedded DVFS Engine.” 2010 IEEE Custom Integrated Circuits Conference (CICC), 2010. 1–4. © Copyright 2012 IEEE
Version
Final published version
Abstract
3GPP LTE requires a 100 Mbps of peak bandwidth, and the instantaneous throughput demand changes with different applications. Fixed sub-block parallel turbo decoding scheme introduces bit-error rate (BER) performance drop when the block length is short. In this paper, an LTE turbo decoder implemented on a 0.66 mm2 die in a 65 nm CMOS technology is presented. An adaptive sub-block parallel (ASP) decoding scheme that improves the BER performance by up to 2.7 dB while maintaining the same parallelism is developed. A DVFS engine combining with an early-termination scheme is also developed. It generates the supply voltage and the clock rate that lead to the lowest energy consumption given the output bandwidth requirement. The measured energy consumption is 0.077~0.168 nJ per bit per iteration and 0.39~0.85 nJ per bit.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/CICC.2010.5617396
